Flash memory device and method of fabricating the same

ABSTRACT

A semiconductor device includes a semiconductor substrate having a cell region and a peripheral region. A cell array is defined within the cell region, the cell array having first, second, third, and fourth sides. A first decoder is defined within the peripheral region and provided adjacent to the first side of the cell array. A first isolation structure is formed at a first boundary region provided between the first side of the cell array and the peripheral region. A first dummy active region is formed at a second boundary region that is provided between the second side of the cell array and the peripheral region. The first isolation structure has a first portion that has a first depth and a second portion that has a second depth.

CROSS-REFERENCES TO RELATED APPLICATIONS

The present application claims priority to Korean patent applicationnumber 2005-72323, filed on Aug. 8, 2005, which is incorporated byreference.

BACKGROUND OF THE INVENTION

The present invention relates to a memory device and method offabricating the same, and more particularly, to forming a boundaryregion between cell and peripheral regions in the memory device.

In the memory device, e.g., the NAND flash, the pitch of the isolationtrench is becoming smaller and smaller as the technology advances. Theisolation trench is gap-filled with an oxide film to form field oxidestructure (FOX) or isolation structure. Such an oxide film is typicallyformed using High Density Plasma (HDP) method. The step-coverage failureof the isolation structure is more likely to occur as the isolationtrench is provided with a smaller pitch.

The step-coverage failure in the memory cell region can be quiteserious. The step-coverage failure may generate a void in the isolationstructure of the memory cell that can affect the reliability of thememory cell. To address this concern, the depth of an isolation trenchof the memory cell region is set to 2000 Å or less in order to improvethe step coverage.

However, the depth of the isolation trench at the peripheral regiontends to be substantially deeper. That is, the voltage applied to theperipheral components of the device generally has not changed even asthe technological advance has greatly reduced the size of the device.Accordingly, a transistor formed in the peripheral region continues tobe provided with a deep isolation trench to withstand a high voltage of20V or more.

Currently a boundary region between the cell region and the peripheralregion is defined by forming a dummy active region or forming anisolation layer. If the dummy active region is formed, a gate oxidelayer thinning phenomenon may occur at an edge of the dummy activeregion. If a high voltage of about 20V is applied to the gate lineduring a NAND flash memory device operation, the gate oxide breakdowncould occur at the thinned-out portion of the gate oxide layer. Thiswould result in device failure.

BRIEF SUMMARY OF THE INVENTION

The present invention relates to forming a boundary between the cell andperipheral regions in a memory device. In one embodiment, asemiconductor device includes a semiconductor substrate having a cellregion and a peripheral region. A cell array is defined within the cellregion, the cell array having first, second, third, and fourth sides. Afirst decoder is defined within the peripheral region and providedadjacent to the first side of the cell array. A first isolationstructure is formed at a first boundary region provided between thefirst side of the cell array and the peripheral region. A first dummyactive region is formed at a second boundary region that is providedbetween the second side of the cell array and the peripheral region. Thefirst isolation structure has a first portion that has a first depth anda second portion that has a second depth.

In another embodiment, a gate line is provided over the first boundaryregion, wherein a gate line is not provided over the second boundaryregion. A well pickup region provided at the second boundary region. Thesubstrate has a well region formed within the cell region, the wellpickup region having a higher dopant concentration than the well regionprovided in the cell region. A second decoder is defined within theperipheral region and provided adjacent to the third side of the cellarray. A second dummy active region is formed at a third boundary regionprovided between the third side of the cell array and the peripheralregion. A second gate line is provided over the third boundary region.

In another embodiment, a method for forming a semiconductor deviceincludes providing a semiconductor substrate having a cell region and aperipheral region. The cell region has a cell array with first, second,third, and fourth sides. The cell array has a first decoder at a firstboundary provided between the first side of the cell array and theperipheral region. A first isolation structure is formed at a firstboundary region defined between the first side of the cell array and theperipheral region. A first dummy active region is formed at a secondboundary region defined between the second side of the cell array andthe peripheral region. A first gate line is formed over the firstboundary region. A well pickup region is formed within the dummy activeregion after the isolation structure and the dummy active region havebeen formed. The well pickup region is formed using the same impurity asthat of a well region formed within the cell region.

In yet another embodiment, the first-isolation-structure is formed byetching a first trench to form a first portion of the first isolationstructure, the first trench having a first depth; and etching a secondtrench to form a second portion of the first isolation structure, thesecond trench having a second depth. The first and second trenchesdefine an abrupt interface that can damage the semiconductor substrateduring a subsequent thermal process.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a cross-sectional view of a flash memory devicehaving an isolation structure at a boundary region between a cell regionand a peripheral region according to one embodiment of the presentinvention.

FIG. 2 illustrates a cross-sectional view of a boundary region of amemory cell region and a peripheral region that would not have a gateline provided over the boundary region according to one embodiment ofthe present invention.

FIG. 3A shows a cell array having a one-side word line (W/L) codingstructure.

FIG. 3B shows boundary regions of a cell array having a one-side W/Lcoding structure according to one embodiment of the present invention;

FIG. 4A shows a cell array having two-side W/L coding structure.

FIG. 4B shows boundary regions of a cell array having two-side W/Lcoding structure according to one embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

The present invention relates to forming a boundary region between acell region and a peripheral region in a memory device, e.g., a NANDflash memory device. The type of the boundary region formed depends onwhether or not a gate line is provided over the boundary regionaccording to embodiments of the present invention. For example, a fieldoxide structure (FOX) is formed if a gate line is provided over theboundary region, and a dummy active region is formed when a gate line isnot provided over the boundary region.

FIG. 1 illustrates a cross-sectional view of a flash memory device 100having an isolation structure 111 b at a boundary region B between acell region A and a peripheral region C according to one embodiment ofthe present invention. The flash memory device 100 has a semiconductorsubstrate 110, a plurality of isolation structures 111 a in the cellregion A, an isolation structure 111 b at the boundary region B, a gateline 112, and a well pickup region 113 in the peripheral region C.

The well pickup region 113 is used to uniformly distribute the biasduring an erase operation of the flash memory device. In the presentembodiment, the well pickup region is formed by implanting the sameimpurity (or dopant), e.g., boron, as that used to form other wellregions on the substrate (e.g., in the cell region). The impurityconcentration of the well pickup region is higher than that of the wellregion in the cell region. For example, the impurity concentration forthe well pickup region is 5E14 to 5E15 ions/cm² in the presentembodiment.

The memory device 100 has the isolation structure (or FOX) 111 b at theboundary region B because the gate line 112 is provided over theboundary region. A gate oxide layer (not shown) formed below the gateline 112 may thin-out at an edge of the boundary region if a dummyactive region is formed at the boundary region. This thinning effect mayresult in the gate oxide breakdown when a high voltage is applied to thegate line.

However, forming a large isolation structure, such as the isolationstructure 111 b, at the boundary region B has certain undesirableeffects. The isolation structure 111 b comprises of a first portion 121a and a second portion 121 b. The first portion 121 a is formed byfilling a first isolation trench associated with the cell region, andthe second portion 121 b is formed by filling a second isolation trenchassociated with the peripheral region. The first and second isolationtrenches have different depths and are formed by using two differentetch steps. As a result, an abrupt “V-like” shape (or interface) 122 isformed at the area where the first and second isolations trenches meet.This abrupt interface 122 may cause defects in the silicon substrateduring the subsequent thermal processes.

In addition, the isolation structure 111 b may experience dishing andform a groove thereon when it is polished due to its large lateral size.Polysilicon residues may be formed within the groove when a self-alignedfloating gate process is performed subsequently. Size of the groovegenerally corresponds to the lateral size of the isolation structure 111b. Accordingly, to minimize the polysilicon residue formation, thelateral size of the isolation structure 111 b (or distance between thememory cell region A and the well pickup region 113) should be reduced.Preferably, the isolation structure 111 b should not be used when itsuse is not necessary.

FIG. 2 illustrates a cross-sectional view of a flash memory device 200having a dummy active region 201 at a boundary region B between a cellregion A and a peripheral region C according to one embodiment of thepresent invention. Note a gate line is not provided over the boundaryregion B unlike in the device 100 in FIG. 1. Accordingly, the dummyactive region is used instead of the isolation structure since there isno risk of the gate oxide breakdown at the boundary region. In thepresent embodiment, the dummy active region is formed at the boundaryregion B when a gate line is not to be formed over the boundary regionB.

Referring back to FIG. 2, the flash memory device 200 has asemiconductor substrate 210, isolation structures 211 a in the cellregion, an isolation structure 211 b in the peripheral region C, a dummyactive region 214 at the boundary region, and a well pickup region 113at the boundary region B.

In the present embodiment, the dummy active region 213 also serves asthe well pickup region 213 to reduce the device size. As explainedabove, the well pickup region is used to uniformly distribute the biasduring an erase operation of the flash memory device. The impurityconcentration of the well pickup region 213 is higher than that of thewell region in the cell region. The impurity concentration of the wellpickup region 213 is 5E14 to 5E15 ions/cm².

The device size can be reduced by forming the well pickup region 213 inthe boundary region B as part of the dummy active region 214. In therelated art, the dummy active region and the well pickup region areformed at separate regions. For example, the dummy active region and thewell pickup region are spaced apart from each other by about 2 μm. Thedevice size can be reduced accordingly if both the dummy active regionand the well pickup region are formed in the same boundary region.

In one embodiment, the dummy active region and the isolation structureare formed at different boundary regions of a cell array. The dummyactive region is formed at a first boundary region (or a first side ofthe cell array) that does not have a gate line provided over it, whereasthe isolation structure is formed at a second boundary region (or asecond side of the cell array) that has a gate line provided over it.That is, a given cell array of a semiconductor device of the presentembodiment has both types of the structures illustrated in FIGS. 1 and 2at different boundary regions.

FIG. 3A shows a memory device 300 having a cell array 302 having aone-side word-line (W/L) coding structure. The cell array 302 has foursides. A decoder 304 is provided in the peripheral region of the memorydevice 300 and adjacent to one of the four sides of the cell array 302.The decoder 304 is an X-decoder.

FIG. 3B shows the formation of a plurality of boundary regions of thecell array 302 according to one embodiment of the present invention. Anisolation structure 312 is formed at the side of the cell array wherethe decoder 304 is provided since a gate line would be provided overthat boundary region. Dummy active regions 314 are formed at other threeboundary regions since the gate line would not be provided over theseboundary regions. A well pickup region (not shown) is provided withinone or more of the dummy active regions in the present embodiment.

FIG. 4A shows a memory device 400 having a cell array 402 having atwo-side word-line (W/L) coding structure. The cell array 402 has foursides. A first decoder 404 is provided at one of the four sides of thecell array 402. A second decoder 406 is provided at another side of thecell array 402. Both of these decoders are provided in the peripheralregions of the memory device 400.

FIG. 4B shows the formation of a plurality of boundary regions of thecell array 402 according to one embodiment of the present invention.First and second isolation structures 412 and 414 are formed at thesides of the cell array where the first and second decoders 404 and 406are formed since gate lines would be provided over those boundaryregions. Dummy active regions 416 are formed at other two boundaryregions since the gate line would not be provided over these boundaryregions. A well pickup region (not shown) is provided within one or moreof the dummy active regions in the present embodiment.

As described above, the embodiments of the present invention has one ormore of the following advantages. First, the gate oxide breakdown isreduced since an isolation structure is formed at a boundary region if agate line is to be provided over that boundary region. Second, a dummyactive region is formed at a boundary region if a gate line is not to beprovided over that boundary region to minimize the likelihood of damageto the semiconductor substrate during a subsequent thermal process.Third, the well pickup region is formed within the dummy active regionto reduce the device size.

The above embodiments of the present invention are illustrative and notlimitative. Various alternatives and equivalents are possible. Theinvention is not limited by the type of deposition, etching, polishing,and patterning steps described herein. Nor is the invention limited toany specific type of semiconductor device. For example, the presentinvention has been described above in terms of a NAND flash memorydevice, but the present invention may be implemented in a NOR flashmemory device or other memory devices. Other additions, subtractions, ormodifications are obvious in view of the present disclosure and areintended to fall within the scope of the appended claims.

1. A semiconductor device, comprising: a semiconductor substrate havinga cell region and a peripheral region; a cell array defined within thecell region, the cell array having first, second, third, and fourthsides; a first decoder defined within the peripheral region and providedadjacent to the first side of the cell array; a first isolationstructure formed at a first boundary region provided between the firstside of the cell array and the peripheral region; and a first dummyactive region formed at a second boundary region provided between thesecond side of the cell array and the peripheral region.
 2. Thesemiconductor device of claim 1, further comprising: a first gate linebeing provided over the first boundary region, wherein the secondboundary region does not have a gate line provided over the secondboundary region, and wherein the first isolation structure has a firstportion that has a first depth and a second portion that has a seconddepth.
 3. The semiconductor device of claim 1, further comprising: agate line being provided over the first boundary region, wherein a gateline is not provided over the second boundary region; and a well pickupregion provided at the second boundary region.
 4. The semiconductordevice of claim 3, wherein the substrate has a well region formed withinthe cell region, the well pickup region having a higher dopantconcentration than the well region provided in the cell region.
 5. Thesemiconductor device of claim 3, further comprising: a second decoderdefined within the peripheral region and provided adjacent to the thirdside of the cell array; a second dummy active region formed at a thirdboundary region provided between the third side of the cell array andthe peripheral region; and a second gate line provided over the thirdboundary region.
 6. The semiconductor device of claim 1, wherein thedevice is a non-volatile memory device.
 7. A method for forming asemiconductor device, the method comprising: providing a semiconductorsubstrate having a cell region and a peripheral region, the cell regionhaving a cell array with first, second, third, and fourth sides, thecell array having a first decoder at a first boundary provided betweenthe first side of the cell array and the peripheral region; forming afirst isolation structure at a first boundary region defined between thefirst side of the cell array and the peripheral region; forming a firstdummy active region at a second boundary region defined between thesecond side of the cell array and the peripheral region; and forming afirst gate line over the first boundary region.
 8. The method of claim7, further comprising: forming a well pickup region within the dummyactive region after the isolation structure and the dummy active regionhave been formed.
 9. The method of claim 8, wherein the well pickupregion is formed using the same impurity as that of a well region formedwithin the cell region.
 10. The method of claim 9, wherein the wellpickup region has a higher impurity concentration than that of the wellregion in the cell region.
 11. The method of claim 9, wherein animpurity concentration of the well pickup region is 5E14 to 5E15ions/cm².
 12. The method of claim 7, wherein the forming thefirst-isolation-structure step comprises: etching a first trench to forma first portion of the first isolation structure, the first trenchhaving a first depth; and etching a second trench to form a secondportion of the first isolation structure, the second trench having asecond depth, wherein the first and second trenches define an abruptinterface that can damage the semiconductor substrate during asubsequent thermal process.
 13. The method of claim 7, furthercomprising: forming a second isolation structure at a third boundaryregion defined between the third side of the cell array and theperipheral region; forming a second dummy active region at a fourthboundary region defined between the fourth side of the cell array andthe peripheral region; and a second gate line provided over the thirdboundary region.
 14. The method of claim 13, wherein a gate line is notprovided over neither the first or second dummy active region.